A multi-slot processor uses multiple independent functional units to process operations in parallel. One common example of a multi-slot processor is a very long instruction word (VLIW) processor. A VLIW instruction packages multiple basic commands or operations into a single instruction. Typically, each such basic command represents a RISC operation and includes an opcode, two source operand definitions, and a result operand definition. The source operand definitions and the result operand definition refer to registers in the register file. During execution of the command, the source operands are read from the particular issue slot by supplying fetch signals to the read ports associated with the issue slot in order to fetch the operands. The functional unit typically receives the operands from these read ports, executes the command according to the opcode, and writes back a result into the register file via the write port associated with the particular issue slot. Alternatively, commands may use fewer than two operands and/or produce no result for the register file.
VLIW processors may include a plurality of instruction slots, also known as issue slots, and each slot may execute one operation of the VLIW instruction. Each slot may have an associated set of functional units, but generally, only one functional unit in a given slot may be used at any given time. Each issue slot is also associated with two read ports and one write port to a register file. The functional units may be pipelined to increase processing speed.
U.S. Pat. No. 6,076,154, issued to Van Eijndhoven et al. on Jun. 13, 2000 and assigned to U.S. Philips Corporation, the disclosure of which is incorporated herein in its entirety, describes a VLIW processor having functional units that are conceptually more than one issue slot wide. These functional units are known as superoperational functional units or, equivalently, super functional units. Super functional units can execute instructions, known as superop instructions or superoperations, that have an opcode and several registers as operands. For example, a transpose instruction uses four input registers and two output registers. Superoperations can be considered to take the computing resources of more than one regular VLIW instruction.